1. Field of the Invention
The present invention relates to an electrically erasable and programmable ROM (referred to as an EEPROM hereinafter), and more particularly, to an EEPROM in which a negative voltage is applied to the control gate for erasure.
2. Description of the Prior Art
A conventional EEPROM is constituted of a peripheral circuit that includes memory cells arranged in matrix form along word lines and bit lines, a row decoder, and a column decoder. Level shifters are arranged between the row decoder and the word lines and between the column decoder and the bit lines, respectively. The write or read or erase operation for each selected memory cell is carried out as in the following. Namely, by virtue of a designation signal of write or read or erase and address signals, a row output and a column output from the row decoder and the column decoder are input to the respective level shifters, and a row signal having a voltage corresponding to the write or read or erase operation and a column signal having a voltage corresponding to the write or read or erase operation are output from the respective level shifters to a designated word line and a designated bit line.
The conventional EEPROM memory cell is constituted of a select transistor consisting of an N-channel MOS transistor and an N-channel MOS transistor having a stacked gate type structure (a laminated structure of a floating gate and a control gate). In order to avoid possible confusion as to the definition of write and erase operations, it will tentatively be defined here that the write operation is one in which electron injection to the floating gate takes place while the erase operation is one in which electron emission from the floating gate takes place, analogous to the case for an EEPROM. In such an EEPROM it is necessary to carry out the erase operation for every memory cell so that the length of the erase time will become of importance when an erase operation for a large number of memory cells is to be carried out. For such a reason, when the connection of the memory cells is of the NOR type, for example, there has been proposed the flash type EEPROM (abbreviated as a flash memory hereinafter) which has at least the function of erasing simultaneously and in a lump all the data written on the memory cells that belong to the same word line (in particular, erasure for each unit, with one row or a plurality of rows as a unit, is called sector erasure). Because of this, the flash memory has an advantage of reducing the cell size due to the reduction in the erasure time in comparison to the conventional EEPROM and the elimination of the necessity for the select transistors.
Such a flash memory is reported, for example, in IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, pp. 1157-1162. According to the report, the memory cell is constituted of a first gate insulating film (thickness of about 10 nm) provided on the surface of a P-type silicon substrate, a floating gate consisting of N.sup.+ -type polycrystalline silicon provided on the gate insulating film, a second gate insulating film (thickness of about 25 nm) provided on the top face of the floating gate, a control gate provided on the gate insulating film, and an N.sup.+ -type source and drain provided on the surface of the silicon substrate in self-alignment with these gates.
The operation of a memory cell with the above-mentioned structure can generally be described as follows. For writing to the memory cell, voltages of 7 V, for example, to the drain, 0 V (ground potential) to the silicon substrate and the source, and 12 V, for example, to the control gate, are applied. Since the floating gate is not connected to an external power supply, its potential is uniquely determined by the ratio of the electrostatic capacities due to the first gate insulating film and the second gate insulating film, and the potentials of the control gate, the source, the drain, and the silicon substrate. Ordinarily, by setting the potential of the control gate to be comparable to the potential of the drain, the injected quantity of the hot electrons (electrons having energies that exceed the energy barrier height of the first gate insulating film) generated by the current that flows between the source and the drain to the floating gate is maximum, so that the aforementioned potential setting is prevalent. As a result, electrons are injected to the floating gate pushing down the potential of the floating gate even to a negative level, and shifts the threshold of the memory cell to the positive direction. Ordinarily, the threshold of the memory cell at this time is set to be about 7 V.
Focusing the attention on one memory cell, the erasure of the memory cell (that is, the erasure of a written data) is to draw the electrons that were injected to the floating gate as in the above from the floating gate. For this purpose, the following method is frequently adopted. That is, a voltage of 12 V, for example, is applied to the source, 0 V (ground potential) is applied to the silicon substrate and the control gate, and the drain is left in the open state. Although the potential of the floating gate is determined uniquely as mentioned above, the floating gate is at a negative potential in the state where the the memory cell is written, so that a potential difference corresponding to this component is added further and a fairly strong electric field (greater than 10 MV/cm at this time) is applied to the first gate insulating film between the source and the floating gate. Under such a strong electric field the Fowler-Nordheim current based on the quantum mechanical tunnel effect flows in the first gate insulating film. Utilizing this effect, electrons are drawn from the floating gate to the source, performing the erasure of the memory cell. For example, in a device of the NOR type, the sources of the memory cells connected to the same word line have a common potential so that when one memory cell is erased, at least the remaining memory cells belonging to the same word line will also be erased.
In the conventional flash memory, the erasure method that draws electrons to the source as described in the above has certain problems which deteriorate the reliability of the cell. At this time, a high voltage in the reverse direction of about 12 V with respect to the P-N junction of the source is applied to the source, which was found to create two problems. A first problem is the junction breakdown and a second problem is the generation of hot holes (holes having energies that exceed the energy barrier height of the first gate insulating film) and their injection into the floating gate which takes place prior to the occurrence of the junction breakdown.
To cope with these problems there have been proposed methods for drawing the electrons from the floating gate without applying a high reverse voltage to the source. According to a first method reported in IEDM Technical Digest, 1990, pp. 111-114, erasure is carried out by applying voltages of 5 V to the source and -12 V to the control gate while leaving the drain in the open state. In this method the voltage applied to the source is low so that the junction breakdown would not be generated. The key point of this method is to push out the electrons accumulated in the floating gate to the source side by the application of a negative voltage to the control gate. On the other hand, according to a second method as reported in IEDM Technical Digest, 1990, pp. 115-118, erasure is carried out by applying 0 V (ground potential) to the control gate and applying positive voltages to the source, the drain, and the silicon substrate. The write operation in this method is realized by applying 0 V (ground potential) to the source, the drain, and the silicon substrate, and applying a positive voltage to the control gate alone. The advantage of this method resides in the fact that the application of a high local electric field to the source can be avoided at the time of write or erase, thereby enhancing the reliability of the memory cell.
Both of the above-mentioned methods do have respective features in enhancing the reliability of the memory cell. Note that the contents of these reports place the emphasis on the memory cells, and make no reference to the peripheral circuits. However, when one considers these reports by including up to the peripheral circuits, the presence of different kinds of problem surfaces up. Thus, in the first method, it becomes necessary to pay attention to the constitution of the elements of the circuit that outputs the voltage of -12 V. For example, in an N-channel MOS transistor that constitutes a level shifter connected to the row decoder, a voltage in the forward direction is to be applied to the source or the drain of the transistor which causes a serious problem. Furthermore, a positive voltage is applied to the source, in this method, at the time of erasure, so that it is necessary to isolate the sources that belong to the adjacent word line in order to carry out the sector erasure, which causes an increase in the cell size. On the other hand, the second method has a drawback in that it is applicable to the NAND type EEPROM alone and is not applicable to the NOR type EEPROM.